? semiconductor components industries, llc, 2006 july, 2006 ? rev. 7 1 publication order number: SN74LS192/d SN74LS192 presettable bcd/decade up/down counter presettable 4-bit binary up/down counter the sn54/74ls192 is an up/down bcd decade (8421) counter and the sn54/74ls193 is an up/down modulo-16 binary counter. separate count up and count down clocks are used and in either counting mode the circuits operate synchronously. the outputs change state synchronous with the low-to-high transitions on the clock inputs. separate terminal count up and terminal count down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. individual preset inputs allow the circuits to be used as programmable counters. both the parallel load (pl ) and the master reset (mr) inputs asynchronously override the clocks. ? low power . . . 95 mw typical dissipation ? high speed . . . 40 mhz typical count frequency ? synchronous counting ? asynchronous master reset and parallel load ? individual preset inputs ? cascading circuitry internally provided note: the flatpak version has the same pinouts (connection diagram) as the dual in-line package. connection diagram dip (top view) 14 13 12 11 10 9 123456 7 16 15 8 v cc p 1 p 0 mr tc d tc u p 2 pl p 3 q 1 q 0 cp d cp u q 2 q 3 gnd pin names loading (note a) high low cp u cp d mr pl p n q n tc d tc u count up clock pulse input count down clock pulse input asynchronous master reset (clear) input asynchronous parallel load (active low) input parallel data inputs flip-flop outputs (note b) terminal count down (borrow) output (note b) terminal count up (carry) output (note b) 0.5 u.l. 0.5 u.l. 0.5 u.l. 0.5 u.l. 0.5 u.l. 10 u.l. 10 u.l. 10 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 5 (2.5) u.l. 5 (2.5) u.l. 5 (2.5) u.l. notes: a. 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. b. the output low drive factor is 2.5 u.l. for military (54) and 5 u.l. for commercial (74) b. temperature ranges. http://onsemi.com presettable bcd/decade up/down counter presettable 4-bit binary up/down counter low power schottky j suffix ceramic case 620-09 n suffix plastic case 648-08 16 1 16 1 ordering information sn54lsxxxj ceramic sn74lsxxxn plastic sn74lsxxxd soic 16 1 d suffix soic case 751b-03 logic symbol v cc = pin 16 gnd = pin 8 5 4 326 7 12 9 10 1 15 11 cp d q 0 q 1 q 2 q 3 tc d p 3 p 2 p 1 p 0 pl cp u tc u 13 mr 14
SN74LS192 http://onsemi.com 2 state diagrams figure 1. figure 2. ls192 logic equations for terminal count ls192 ls193 count up count down 01234 5 6 7 8 9 10 11 12 13 14 15 01234 5 6 7 8 9 10 11 12 13 14 15 figure 3. tc u = q 0 ? q 3 ? cp u tc d = q 0 ? q 1 ? q 2 ? q 3 ? cp d figure 4. ls193 logic equations for terminal count figure 5. tc u = q 0 ? q 1 ? q 2 ? q 3 ? cp u tc d = q 0 ? q 1 ? q 2 ? q 3 ? cp d logic diagrams v cc = pin 16 gnd = pin 8 = pin numbers ls192 p 0 p 1 p 2 p 3 tc u (carry output) q 0 q 1 q 2 q 3 mr (clear) (down count) cp d (up count) cp u (load) p l 1 2 67 3 4 5 9 11 12 10 13 15 14 tc d (borrow output) s d q q c d t s d q q c d t s d q q c d t s d q q c d t
SN74LS192 http://onsemi.com 3 logic diagrams (continued) v cc = pin 16 gnd = pin 8 = pin numbers ls193 p 0 p 1 p 2 p 3 q 0 q 1 q 2 q 3 mr (clear) (down count) cp d (up count) cp u (load) p l 1 2 67 3 4 5 9 11 12 10 13 15 14 s d q q c d t s d q q c d t s d q q c d t s d q q c d t tc u (carry output) tc d (borrow output) functional description the ls192 and ls193 are asynchronously presettable decade and 4-bit binary synchronous up / down (reversable) counters. the operating modes of the ls192 decade counter and the ls193 binary counter are identical, with the only dif ference being the count sequences as noted in the state diagrams. each circuit contains four master/slave flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. each flip-flop contains jk feedback from slave to master such that a low -to-high transition on its t input causes the slave, and thus the q output to change state. synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common count up line and a common count down line, thereby causing all state changes to be initiated simultaneously. a low-to-high transition on the count up input will advance the count by one; a similar transition on the count down input will decrease the count by one. while counting with one clock input, the other should be held high. otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is low. the terminal count up (tc u ) and terminal count down (tc d ) outputs are normally high. when a circuit has reached the maximum count state (9 for the ls192, 15 for the ls193), the next high-to-low transition of the count up clock will cause tc u to go low. tc u will stay low until cp u goes high again, thus effectively repeating the count up clock, but delayed by two gate delays. similarly, the tc d output will go low when the circuit is in the zero state and the count down clock goes low. since the tc outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. each circuit has an asynchronous parallel load capability permitting the counter to be preset. when the parallel load (pl ) and the master reset (mr) inputs are low, i nformation present on the parallel data inputs (p 0 , p 3 ) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. a high signal on the master reset input will disable the preset gates, override both clock inputs, and latch each q output in the low state. if one of the clock inputs is low during and after a reset or load operation, the next low -to-high transition of that clock will be interpreted as a legitimate signal and will be counted.
SN74LS192 http://onsemi.com 4 mode select table mr pl cp u cp d mode h x x x reset (asyn.) l l x x preset (asyn.) l h h h no change l h h count up l h h count down l = low voltage level h = high voltage level x = don?t care = low-to-high clock transition guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 v t a operating ambient temperature range 54 74 ? 55 0 25 25 125 70 c i oh output current ? high 54, 74 ? 0.4 ma i ol output current ? low 54 74 4.0 8.0 ma dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions min typ max v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 54 0.7 v guaranteed input low voltage for all inputs 74 0.8 v ik input clamp diode voltage ? 0.65 ? 1.5 v v cc = min, i in = ? 18 ma v oh output high voltage 54 2.5 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table 74 2.7 3.5 v v ol output low voltage 54, 74 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in = v il or v ih per truth table 74 0.35 0.5 v i ol = 8.0 ma i ih input high current 20 a v cc = max, v in = 2.7 v 0.1 ma v cc = max, v in = 7.0 v i il input low current ? 0.4 ma v cc = max, v in = 0.4 v i os short circuit current (note 1) ? 20 ? 100 ma v cc = max i cc power supply current 34 ma v cc = max note 1: not more than one outpu t should be shorted at a time, nor for more than 1 second.
SN74LS192 http://onsemi.com 5 ac characteristics (t a = 25 c) symbol parameter limits unit test conditions min typ max f max maximum clock frequency 25 32 mhz v cc = 5.0 v c l = 15 pf t plh t phl cp u input to tc u output 17 18 26 24 ns t plh t phl cp d input to tc d output 16 15 24 24 ns t plh t phl clock to q 27 30 38 47 ns t plh t phl pl to q 24 25 40 40 ns t phl mr input to any output 23 35 ns ac setup requirements (t a = 25 c) symbol parameter limits unit test conditions min typ max t w any pulse width 20 ns v cc = 5.0 v t s data setup time 20 ns t h data hold time 5.0 ns t rec recovery time 40 ns definitions of terms setup time (t s ) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the pl transition from low-to-high in order to be recognized and transferred to the outputs. hold time (t h ) is defined as the minimum time following the pl transition from low-to-high that the logic level must be maintained at the input in order to ensure continued recognition. a negative hold time indicates that the correct logic level may be released prior to the pl transition from low-to-high and still be recognized. recovery time (t rec ) is defined as the minimum time required between the end of the reset pulse and the clock transition from low-to-high in order to recognize and transfer high data to the q outputs.
SN74LS192 http://onsemi.com 6 ac waveforms figure 1 figure 2 figure 3 figure 4 figure 5 figure 6 figure 7 1.3 v cp u or cp d cp u or cp d cp u or cp d q q q t w cp u or cp d tc u or tc d pl pl p n q n mr t phl t plh t plh p n q n note: pl = low t w t phl p n pl q n t s(h) t s(l) t h(h) t h(l) * the shaded areas indicate when the input is permitted * to change for predictable output performance q = p q = p t plh t rec t plh t phl t phl t w t phl t phl t w 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t rec
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